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| M28F410 M28F420 4 Megabit (x8 or x16, Block Erase) FLASH MEMORY PRELIMINARY DATA DUAL x8 and x16 ORGANIZATION SMALL SIZE PLASTIC PACKAGES TSOP56 and SO44 MEMORY ERASE in BLOCKS - One 16K Byte or 8K Word Boot Block (top or bottom location) with hardware write and erase protection - Two 8K Byte or 4K Word Key Parameter Blocks - One 96K Byte or 48K Word Main Block - Three 128K Byte or 64K Word Main Blocks 5V 10% SUPPLY VOLTAGE 12V 5% PROGRAMMING VOLTAGE 100,000 PROGRAM/ERASE CYCLES PROGRAM/ERASE CONTROLLER AUTOMATIC STATIC MODE LOW POWER CONSUMPTION - 60A Typical in Standby - 0.2A Typical in Deep Power Down - 20/25mA Typical Operating Consumption (Byte/Word) HIGH SPEED ACCESS TIME: 70ns EXTENDED TEMPERATURE RANGES 44 1 TSOP56 (N) 14 x 20mm SO44 (M) Figure 1. Logic Diagram VCC VPP 18 A0-A17 15 RP DQ0-DQ14 M28F410 M28F420 BYTE DQ15A-1 Table 1. Signal Names A0-A17 DQ0-DQ7 DQ8DQ14 DQ15A-1 E G W BYTE RP VPP VCC March 1995 Address Inputs Data Input / Outputs Data Input / Outputs Data Input/Output or Address Input Chip Enable Output Enable Write Enable Byte/Word Organization Reset/Power Down/Boot Block Unlock Program & Erase Supply Voltage Supply Voltage W E G VSS AI01130C 1/38 This is preliminary infor mationon a new product now in developmen t or undergoing evaluation. Details are subject to change without notice. M28F410, M28F420 Figure 2A. TSOP Pin Connections NC NC A15 A14 A13 A12 A11 A10 A9 A8 NC NC W RP NC NC VPP DU NC A17 A7 A6 A5 A4 A3 A2 A1 NC 1 56 NC A16 BYTE VSS DQ15A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0 NC NC Figure 2B. SO Pin Connections 14 15 M28F410 M28F420 (Normal) 43 42 VPP DU A17 A7 A6 A5 A4 A3 A2 A1 A0 E VSS G DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 44 1 2 43 3 42 4 41 5 40 6 39 7 38 8 37 9 36 10 35 11 M28F410 34 12 M28F420 33 13 32 14 31 15 30 16 29 17 28 18 27 19 26 20 25 24 21 22 23 AI01133C RP W A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE VSS DQ15A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC 28 29 AI01132C Warning: NC = Not Connected, DU = Don't Use Warning: DU = Don't Use Table 2. Absolute Maximum Ratings (1) Symbol TA Parameter Ambient Operating Temperature grade 1 grade 3 grade 6 Value 0 to 70 -40 to 125 -40 to 85 -50 to 125 -65 to 150 -0.6 to 7 -0.6 to 7 -0.6 to 13.5 -0.6 to 14 -0.6 to 13.5 Unit C C C V V V V V TBIAS TSTG VIO (2, 3) Temperature Under Bias Storage Temperature Input or Output Voltages Supply Voltage A9 Voltage Program Supply Voltage, during Erase or Programming RP Voltage VCC VA9 (2) VPP (2) VRP (2) Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents. 2. Minimum Voltage may undershoot to -2V during transition and for less than 20ns. 3. Maximum DC voltage on I/O is VCC + 0.5V, overshoot to 7V allowed for less than 20ns. 2/38 M28F410, M28F420 Table 3. Operations Operation Read Word Read Byte Write Word Write Byte Output Disable Standby Power Down E VIL VIL VIL VIL VIL VIH X G VIL VIL VIH VIH VIH X X W VIH VIH VIL VIL VIH X X RP VIH VIH VIH VIH VIH VIH VIL BYTE VIH VIL VIH VIL X X X DQ0 - DQ7 Data Output Data Output Data Input Data Input Hi-Z Hi-Z Hi-Z DQ8 - DQ14 Data Output Hi-Z Data Input Hi-Z Hi-Z Hi-Z Hi-Z DQ15A-1 Data Output Address Input Data Input Address Input Hi-Z Hi-Z Hi-Z Note: X = VIL or VIH, VPP = VPPL or VPPH Table 4. Electronic Signature Organisation Code Manufact. Code Wordwide Device Code M28F410 M28F420 Manufact. Code Bytewide Device Code M28F410 M28F420 Note: RP = VIH Device E VIL VIL VIL VIL VIL VIL G VIL VIL VIL VIL VIL VIL W VIH VIH VIH VIH VIH VIH BYTE VIH VIH VIH VIL VIL VIL A0 VIL VIH VIH VIL VIH VIH A9 VID VID VID VID VID VID A1-A8 & A10-A17 Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care DQ0 DQ7 20h 0F2h 0FAh 20h 0F2h 0FAh DQ8 DQ14 00h 00h 00h Hi-Z Hi-Z Hi-Z DQ15 A-1 0 0 0 Don't Care Don't Care Don't Care DESCRIPTION The M28F410 and M28F420 FLASH MEMORIES are non-volatile memories that may be erased electrically at the block level and programmed by byte or word. The interface is directly compatible with most microprocessors. SO44 and TSOP56 packages are used. Organization The organization, as 512K x 8 or 256K x 16, is selectable by an external BYTE signal. When BYTE is Low and the x8 organization is selected, the Data Input/Outputsignal DQ15 acts as Address line A-1 and selects the lower or upper byte of the memory word for output on DQ0-DQ7, DQ8-DQ14 remain high impedance. When BYTE is High the memory uses the Address inputs A0-A17 and the Data Input/OutputsDQ0-DQ15. Memory control is provided by Chip Enable, Output Enable and Write Enable inputs. A Reset/Power Down/Boot block unlock, tri-level input, places the memory in deep power down, normal operation or enables programming and erasure of the Boot block. 3/38 M28F410, M28F420 Table 5. Instructions Mnemonic Instruction Read Memory Array Read Status Register Read Electronic Signature Erase Program Clear Status Register Erase Suspend Erase Resume Cycles Operation 1+ Write 1st Cycle Address (1) X Data (4) 0FFh Operation Read (2) 2nd Cycle Address Read Address Data Data RD RSR 1+ Write X 70h Read (2) X Status Register RSIG 3 Write X 90h Read (2) Signature (3) Adress Block Address Address Signature EE PG CLRS 2 2 1 Write Write Write X X X 20h 40h or 10h 50h Write Write 0D0h Data Input ES ER 1 1 Write Write X X 0B0h 0D0h Notes: 1. X = Don't Care. 2. The first cycle of the RD, RSR or RSIG instruction is followed by read operations to read memory array, Status Register or Electronic Signature codes. Any number of Read cycle can occur after one command cycle. 3. Signature address bit A0=VIL will output Manufacturer code. Address bit A0=VIH will output Device code. Other address bits are ignored. 4. When word organization is used, upper byte is don't care for command input. Table 6. Commands Hex Code 00h 10h 20h 40h 50h 70h 90h 0B0h 0D0h 0FFh Command Invalid/Reserved Alternative Program Set-up Erase Set-up Program Set-up Clear Status Register Read Status Register Read Electronic Signature Erase Suspend Erase Resume/Erase Confirm Read Array Blocks Erasure of the memories is in blocks. There are 7 blocks in the memory address space, one Boot Block of 16K Bytes or 8K Words, two 'Key Parameter Blocks' of 8K Bytes or 4K Words, one 'Main 4/38 Block' of 96K Bytes or 48K Words, and three 'Main Blocks'of 128KBytes or 64K Words. The M28F410 memory has the Boot Block at the top of the memory address space (3FFFFh) and the M28F420 locates the Boot Block starting at the bottom (00000h). Erasure of each block takes typically 1 second and each block can be programmed and erased over 100,000 cycles. The Boot Block is hardware protected from accidental programming or erasure depending on the RP signal. Program/Erase commands in the Boot Block are executed only when RP is at 12V. Block erasure may be suspended while data is read from other blocks of the memory, then resumed. Bus Operations Six operationscan beperformed by the appropriate bus cycles, Read Byte or Word from the Array, Read Electronic Signature, Output Disable, Standby, Power Down and Write the Command of an Instruction. Command Interface Commands can be written to a Command Interface (C.I.) latch to perform read, programming, erasure and to monitor the memory's status. When power M28F410, M28F420 Table 7. Status Register Mnemonic Bit Name Logic Level '1' P/ECS 7 P/E.C. Status '0' Erase Suspend Status '1' '0' '1' ES 5 Erase Status '0' '1' '0' '1' VPPS 3 VPP Status '0' 2 1 0 Reserved Reserved Reserved VPP OK Erase Success Program Error Program Success VPP Low, Abort Busy Suspended In progress or Completed Erase Error Definition Ready Note Indicates the P/E.C. status, check during Program or Erase, and on completion before checking bits b4 or b5 for Program or Erase Success On an Erase Suspend instruction P/ECS and ESS bits are set to '1'. ESS bit remains '1' until an Erase Resume instruction is given. ESS 6 ES bit is set to '1' if P/E.C. has applied the maximum number of erase pulses to the block without achieving an erase verify. PS 4 Program Status PS bit set to '1' if the P/E.C. has failed to program a byte or word. VPPS bit is set if the VPP voltage is below VPPH(min) when a Program or Erase instruction has been executed. Notes: Logic level '1' is High, '0' is Low. is first applied, on exit from power down or if VCC falls below VLKO , the command interface is reset to Read Memory Array. Instructions and Commands Eight Instructions are defined to perform Read Memory Array, Read Status Register, Read Electronic Signature, Erase, Program, Clear Status Register, Erase Suspend and Erase Resume. An internalProgram/EraseController (P/E.C.) handles all timing and verification of the Program and Erase instructions and provides status bits to indicate its operation and exit status. Instructions are composed of a first command write operation followed by either second command write, to confirm the commands for programming or erase, or a read operationto read data from the array, the Electronic Signature or the Status Register. For added data protection, the instructions for byte or word program and block erase consist of two commands that are written to the memory and which start the automatic P/E.C. operation. Byte or word programming takes typically 9s, block erase typically 1 second. Erasure of a memory block may be suspended in order to read data from another block and then resumed. A Status Register may be read at any time, including during the programming or erase cycles, to monitor the progress of the operation. Power Saving The M28F410 and M28F420 have a number of power saving features. A CMOS standby mode is entered when the Chip Enable E and the Reset/Power Down (RP) signals are at VCC, when the supply current drops to typically 60A. A deep power down mode is enabled when the Reset/Power Down (RP) signal is at VSS, when the supply current drops to typically 0.2A. The time required to awake from the deep power down mode is 300ns maximum, with instructions to the C.I. recognised after only 210ns. 5/38 M28F410, M28F420 Table 8. AC Measurement Conditions SRAM Interface Levels Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 10ns 0 to 3V 1.5V EPROM Interface Levels 10ns 0.45V to 2.4V 0.8V and 2V Figure 3. AC Testing Input Output Waveform Figure 4. AC Testing Load Circuit 1.3V SRAM Interface 3V 1.5V 0V DEVICE UNDER TEST 2.0V 0.8V AI01275 1N914 3.3k EPROM Interface 2.4V OUT CL = 30pF or 100pF 0.45V CL = 30pF for SRAM Interface CL = 100pF for EPROM Interface CL includes JIG capacitance AI01276 Table 9. Capacitance (1) (TA = 25 C, f = 1 MHz ) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 12 Unit pF pF Note: 1. Sampled only, not 100% tested. DEVICE OPERATION Signal Descriptions A0-A17 Address Inputs. The address signals, inputs for the memory array, are latched during a write operation. A9 Address Input is also used for the Electronic Signature Operation. When A9 is raised to 12V the Electronic Signature may be read. The A0 signal is used to read two words or bytes, when A0 is Low the Manufacturercode is read and when A0 is High the Device code. When BYTE is Low DQ0-DQ7 output the codes and DQ8-DQ15 are don't care, when BYTE is High DQ0-DQ7 output the codes and DQ8-DQ15 output 00h. 6/38 DQ0-DQ7 Data Input/Outputs. The data inputs, a byte or the lower byte of a word to be programmed or a command to the C.I., are latched when both Chip Enable E and Write Enable W are active. The data output from the memory Array, the Electronic Signature or Status Register is valid when Chip Enable E and Output Enable G are active. The output is high impedance when the chip is deselected or the outputs are disabled. DQ8-DQ14 and DQ15A-1 Data Input/Outputs. These input/outputs are used in the word-wide organization. When BYTE is High for the most significant byte of the input or output, functioning as described for DQ0-DQ7 above. When BYTE is Low, DQ8-DQ14 are high impedance, DQ15A-1 is the Address A-1 input. M28F410, M28F420 Table 10. DC Characteristics (TA = 0 to 70C; VCC = 5V10% or 5V5% ; VPP = 12V5%) Symbol ILI ILO ICC (1, 3) ICC ICC (1, 3) Parameter Input Leakage Current Output Leakage Current Supply Current (Read Byte-wide) TTL Supply Current (Read Word-wide) TTL Supply Current (Read Byte-wide) CMOS Test Condition 0V VIN VCC 0V VOUT VCC E = VIL, f = 10MHz, IOUT = 0mA E = VIL, f = 10MHz, IOUT = 0mA E = VSS, f = 10MHz, IOUT = 0mA E = VSS, f = 10MHz, IOUT = 0mA E = VIH , RP = VIH E = VCC 0.2V, RP = VCC 0.2V, BYTE = VCC 0.2V or VSS RP = VSS 0.2V Byte program in progress Word program in progress Erase in progress E = VIH, Erase suspended VPP > VCC VPP VCC RP = VSS 0.2V Byte program in progress Word program in progress Erase in progress Erase suspended Min Max 1 10 50 55 45 50 3 100 5 50 60 30 10 200 10 5 30 40 30 200 Unit A A mA mA mA mA mA A A mA mA mA mA A A A mA mA mA A V V V V (1, 3) Supply Current (Read Word-wide) CMOS Supply Current (Standby) TTL (3) ICC1 Supply Current (Standby) CMOS ICC2 (3) Supply Current (Power Down) Supply Current (Program Byte-wide) Supply Current (Program Word-wide) ICC3 ICC4 ICC5 (2) Supply Current (Erase) Supply Current (Erase Suspend) Program Current (Read or Standby) Program Leakage Current (Read or Standby) Program Current (Power Down) Program Current (Program Byte-wide) Program Current (Program Word-wide) Program Current (Erase) Program Current (Erase Suspend) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Program Voltage (Normal operation) Program Voltage (Program or Erase operations) A9 Voltage (Electronic Signature) A9 Current (Electronic Signature) Supply Voltage (Erase and Program lock-out) Input Voltage (RP, Boot unlock) IPP IPP1 IPP2 IPP3 IPP3 IPP4 IPP5 VIL VIH VOL VOH VPPL VPPH VID IID VLKO VHH -0.5 2 IOL = 5.8mA IOH = -2.5mA 2.4 0 11.4 11.4 A9 = VID 2 Boot block Program or Erase 11.4 0.8 VCC + 0.5 0.45 6.5 12.6 13 500 V V V A V 13 V Notes: 1. Automatic Power Saving reduces ICC to 8mA typical in static operation. 2. Current increases to ICC + ICC5 during a read operation. 3. CMOS levels VCC 0.2V and VSS 0.2V. TTL levels VIH and VIL. 7/38 M28F410, M28F420 Table 11. DC Characteristics (TA = -40 to 85C; VCC = 5V10% or 5V5% ; VPP = 12V5%) Symbol ILI ILO ICC (1, 3) ICC ICC (1, 3) Parameter Input Leakage Current Output Leakage Current Supply Current (Read Byte-wide) TTL Supply Current (Read Word-wide) TTL Supply Current (Read Byte-wide) CMOS Test Condition 0V VIN VCC 0V VOUT VCC E = VIL, f = 10MHz, IOUT = 0mA E = VIL, f = 10MHz, IOUT = 0mA E = VSS, f = 10MHz, IOUT = 0mA E = VSS, f = 10MHz, IOUT = 0mA E = VIH, RP = VIH E = VCC 0.2V, RP = VCC 0.2V, BYTE = VCC 0.2V or VSS RP = VSS 0.2V Byte program in progress Word program in progress Erase in progress E = VIH, Erase suspended VPP > VCC VPP VCC RP = VSS 0.2V Byte program in progress Word program in progress Erase in progress Erase suspended Min Max 1 10 65 70 60 65 3 100 8 50 60 30 10 200 15 5 30 40 30 200 Unit A A mA mA mA mA mA A A mA mA mA mA A A A mA mA mA A V V V V (1, 3) Supply Current (Read Word-wide) CMOS Supply Current (Standby) TTL (3) ICC1 Supply Current (Standby) CMOS ICC2 (3) Supply Current (Power Down) Supply Current (Program Byte-wide) Supply Current (Program Word-wide) ICC3 ICC4 ICC5 (2) Supply Current (Erase) Supply Current (Erase Suspend) Program Current (Read or Standby) Program Leakage Current (Read or Standby) Program Current (Power Down) Program Current (Program Byte-wide) Program Current (Program Word-wide) Program Current (Erase) Program Current (Erase Suspend) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Program Voltage (Normal operation) Program Voltage (Program or Erase operations) A9 Voltage (Electronic Signature) A9 Current (Electronic Signature) Supply Voltage (Erase and Program lock-out) Input Voltage (RP, Boot unlock) IPP IPP1 IPP2 IPP3 IPP3 IPP4 IPP5 VIL VIH VOL VOH VPPL VPPH VID IID VLKO VHH -0.5 2 IOL = 5.8mA IOH = -2.5mA 2.4 0 11.4 11.4 A9 = VID 2 Boot block Program or Erase 11.4 0.8 VCC + 0.5 0.45 6.5 12.6 13 500 V V V A V 13 V Notes: 1. Automatic Power Saving reduces ICC to 8mA typical in static operation. 2. Current increases to ICC + ICC5 during a read operation. 3. CMOS levels VCC 0.2V and VSS 0.2V. TTL levels VIH and VIL. 8/38 M28F410, M28F420 Table 12. DC Characteristics (TA = -40 to 125C; VCC = 5V10% or 5V5% ; VPP = 12V5%) Symbol ILI ILO ICC (1, 3) ICC ICC (1, 3) Parameter Input Leakage Current Output Leakage Current Supply Current (Read Byte-wide) TTL Supply Current (Read Word-wide) TTL Supply Current (Read Byte-wide) CMOS Test Condition 0V VIN VCC 0V VOUT VCC E = VIL, f = 10MHz, IOUT = 0mA E = VIL, f = 10MHz, IOUT = 0mA E = VSS, f = 10MHz, IOUT = 0mA E = VSS, f = 10MHz, IOUT = 0mA E = VIH, RP = VIH E = VCC 0.2V, RP = VCC 0.2V, BYTE = VCC 0.2V or VSS RP = VSS 0.2V Byte program in progress Word program in progress Erase in progress E = VIH, Erase suspended VPP > VCC VPP VCC RP = VSS 0.2V Byte program in progress Word program in progress Erase in progress Erase suspended Min Max 1 10 65 70 60 65 3 130 80 50 60 30 10 200 10 5 30 40 30 200 Unit A A mA mA mA mA mA A A mA mA mA mA A A A mA mA mA A V V V V (1, 3) Supply Current (Read Word-wide) CMOS Supply Current (Standby) TTL (3) ICC1 Supply Current (Standby) CMOS ICC2 (3) Supply Current (Power Down) Supply Current (Program Byte-wide) Supply Current (Program Word-wide) ICC3 ICC4 ICC5 (2) Supply Current (Erase) Supply Current (Erase Suspend) Program Current (Read or Standby) Program Leakage Current (Read or Standby) Program Current (Power Down) Program Current (Program Byte-wide) Program Current (Program Word-wide) Program Current (Erase) Program Current (Erase Suspend) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Program Voltage (Normal operation) Program Voltage (Program or Erase operations) A9 Voltage (Electronic Signature) A9 Current (Electronic Signature) Supply Voltage (Erase and Program lock-out) Input Voltage (RP, Boot unlock) IPP IPP1 IPP2 IPP3 IPP3 IPP4 IPP5 VIL VIH VOL VOH VPPL VPPH VID IID VLKO VHH -0.5 2 IOL = 5.8mA IOH = -2.5mA 2.4 0 11.4 11.4 A9 = VID 2 Boot block Program or Erase 11.4 0.8 VCC + 0.5 0.45 6.5 12.6 13 500 V V V A V 13 V Notes: 1. Automatic Power Saving reduces ICC to 8mA typical in static operation. 2. Current increases to ICC + ICC5 during a read operation. 3. CMOS levels VCC 0.2V and VSS 0.2V. TTL levels VIH and VIL. 9/38 M28F410, M28F420 Table 13. Read AC Characteristics (1) (TA = 0 to 70C or -40 to 85C; VPP = 12V 5%) M28F410 / 20 -70 Symbol Alt Parameter VCC = 5V 5% SRAM Interface Min tAVAV tAVQV tPHQV tELQX (2) -80 -100 -120 Unit VCC = 5V 10% VCC = 5V 10% VCC = 5V 10% EPROM Interface Min 80 Max EPROM Interface Min 100 80 300 0 0 80 0 0 40 0 0 30 0 0 30 0 0 35 0 35 0 35 45 0 35 100 0 50 100 300 0 120 Max EPROM Interface Min 120 120 300 Max Max tRC tACC tPWH tLZ tCE tOLZ tOE tOH tHZ tOH tDF tOH Address Valid to Next Address Valid Address Valid to Output Valid Power Down High to Output Valid Chip Enable Low to Output Transition Chip Enable Low to Output Valid Output Enable Low to Output Transition Output Enable Low to Output Valid Chip Enable High to Output Transition Chip Enable High to Output Hi-Z Output Enable High to Output Transition Output Enable High to Output Hi-Z Address Transition to Output Transition 70 70 300 0 70 0 35 0 25 0 25 0 ns ns ns ns ns ns ns ns ns ns ns ns tELQV (3) tGLQX tGLQV tEHQX tEHQZ tGHQX tGHQZ tAXQX (2) (3) (2) (2) (2) (2) (2) Notes: 1. See Figure 3 and Table 8 for timing measurements. 2. Sampled only, not 100% tested. 3. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV. 10/38 M28F410, M28F420 Table 14. Read AC Characteristics (1) (TA = -40 to 125C; VPP = 12V 5%) M28F410 / 20 -80 Symbol Alt Parameter VCC = 5V 5% SRAM Interface Min tAVAV tAVQV tPHQV tELQX (2) -90 -100 -120 Unit VCC = 5V 10% VCC = 5V 10% VCC = 5V 10% EPROM Interface Min 90 Max EPROM Interface Min 100 90 300 0 0 90 0 0 45 0 0 35 0 0 35 0 0 40 0 40 0 45 50 0 45 100 0 55 100 300 0 120 Max EPROM Interface Min 120 120 300 Max Max tRC tACC tPWH tLZ tCE tOLZ tOE tOH tHZ tOH tDF tOH Address Valid to Next Address Valid Address Valid to Output Valid Power Down High to Output Valid Chip Enable Low to Output Transition Chip Enable Low to Output Valid Output Enable Low to Output Transition Output Enable Low to Output Valid Chip Enable High to Output Transition Chip Enable High to Output Hi-Z Output Enable High to Output Transition Output Enable High to Output Hi-Z Address Transition to Output Transition 80 80 300 0 80 0 40 0 30 0 30 0 ns ns ns ns ns ns ns ns ns ns ns ns tELQV (3) tGLQX tGLQV tEHQX tEHQZ tGHQX tGHQZ tAXQX (2) (3) (2) (2) (2) (2) (2) Notes: 1. See Figure 3 and Table 8 for timing measurements. 2. Sampled only, not 100% tested. 3. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV. 11/38 12/38 tAVAV VALID tAVQV tAXQX tELQV tELQX tEHQZ tEHQX tGLQV tGLQX VALID tGHQX tGHQZ OUTPUTS ENABLED DATA VALID STANDBY AI01281B M28F410, M28F420 A-1, A0-A17 A Figure 5. Read Mode AC Waveforms E G DQ0-DQ15 tPHQV RP POWER-UP AND STANDBY ADDRESS VALID AND CHIP ENABLE Note: Write Enable (W) = High M28F410, M28F420 Table 15. BYTE AC Characteristics (1) (TA = 0 to 70C or -40 to 85C; VPP = 12V 5%) M28F410 / 20 -70 Symbol Parameter VCC = 5V 5% SRAM Interface Min tELBL tELBH tBLQV (2) tBHQV tBLQZ Chip Enable Low to BYTE Low Chip Enable Low to BYTE High BYTE Low to Output Valid BYTE High to Output Valid BYTE Low to Output Hi-Z Max 5 5 70 70 25 -80 VCC = 5V 10% EPROM Interface Min Max 5 5 80 80 30 -100 VCC = 5V 10% EPROM Interface Min Max 5 5 100 100 35 -120 VCC = 5V 10% EPROM Interface Min Max 5 5 120 120 35 ns ns ns ns ns Unit Notes: 1. Sampled only, not 100% tested. 2. It is equal to tAVQV when measured from DQ15A-1 valid. Table 16. BYTE AC Characteristics (1) (TA = -40 to 125C; VPP = 12V 5%) M28F410 / 20 -80 Symbol Parameter VCC = 5V 5% SRAM Interface Min tELBL tELBH tBLQV (2) tBHQV tBLQZ Chip Enable Low to BYTE Low Chip Enable Low to BYTE High BYTE Low to Output Valid BYTE High to Output Valid BYTE Low to Output Hi-Z Max 5 5 80 80 30 -90 VCC = 5V 10% EPROM Interface Min Max 5 5 90 90 35 -100 VCC = 5V 10% EPROM Interface Min Max 5 5 100 100 40 -120 VCC = 5V 10% EPROM Interface Min Max 5 5 120 120 45 ns ns ns ns ns Unit Notes: 1. Sampled only, not 100% tested. 2. It is equal to tAVQV when measured from DQ15A-1 valid. 13/38 M28F410, M28F420 Figure 6. BYTE Mode AC Waveforms, BYTE Low to High A0-A17 VALID E tELBH BYTE tBHQV DQ0-DQ14 VALID DQ0-DQ7 VALID DQ0-DQ14 DQ15A-1 VALID A-1 VALID DQ15 BYTE READ WORD/BYTE TRANSITION WORD READ AI01282 Note: G Low, W = High, other timings as Read Mode AC waveforms. Figure 7. BYTE Mode AC Waveforms, BYTE High to Low A0-A17 VALID E tELBL BYTE tBLQV DQ0-DQ14 VALID DQ0-DQ14 tBLQZ DQ15A-1 VALID DQ15 Hi-Z VALID A-1 VALID DQ0-DQ7 WORD READ WORD/BYTE TRANSITION BYTE READ AI01283B Note: G Low, W = High, other timings as Read Mode AC waveforms. 14/38 M28F410, M28F420 Table 17A. Write AC Characteristics, Write Enable Controlled (1) (TA = 0 to 70C or -40 to 85C; VPP = 12V 5%) M28F410 / 20 -70 Symbol Alt Parameter VCC = 5V 5% SRAM Interface Min tAVAV tPHWL tELWL tWLWH tDVWH tWHDX tWHEH tWHWL tAVWH tPHHWH tVPHWH (5) -80 VCC = 5V 10% EPROM Interface Min 80 210 0 50 50 0 10 30 50 100 100 10 6 0.3 0.3 0.6 0 0 100 100 Max ns ns ns ns ns ns ns ns ns ns ns ns s sec sec sec ns ns ns Unit Max tWC tPS tCS tWP tDS tDH tCH Write Cycle Time Power Down High to Write Enable Low Chip Enable Low to Write Enable Low Write Enable Low to Write Enable High Data Valid to Write Enable High Write Enable High to Data Transition Write Enable High to Chip Enable High 70 210 0 50 50 0 10 20 50 100 100 10 6 0.3 0.3 0.6 0 0 tWPH Write Enable High to Write Enable Low tAS tPHS tVPS tAH Address Valid to Write Enable High Power Down VHH (Boot Block Unlock) to Write Enable High VPP High to Write Enable High Write Enable High to Address Transition Write Enable High to Output Valid (Word/Byte Program) Write Enable High to Output Valid (Boot Block Erase) Write Enable High to Output Valid (Parameter Block Erase) Write Enable High to Output Valid (Main Block Erase) tPHH Output Valid to Reset/Power Down High Output Valid to VPP Low Reset/Power Down High to Boot Block Relock (5) tWHAX tWHQV1 (2, 3) tWHQV2 (2, 3) tWHQV3 tWHQV4 (2) (2) tQVPH (5) tQVVPL (5) tPHBR (4, 5) Notes: 1. 2. 3. 4. 5. See Figure 3 and Table 8 for timing measurements. Time is measured to Status Register Read giving bit b7 = '1'. For Program or Erase of the Boot Block RP must be at VHH. Time required for Relocking the Boot Block. Sampled only, not 100% tested. 15/38 M28F410, M28F420 Table 17B. Write AC Characteristics, Write Enable Controlled (1) (TA = 0 to 70C or -40 to 85C; VPP = 12V 5%) M28F410 / 420 -100 Symbol Alt Parameter VCC = 5V 10% EPROM Interface Min tAVAV tPHWL tELWL tWLWH tDVWH tWHDX tWHEH tWHWL tAVWH tPHHWH tVPHWH (5) -120 VCC = 5V 10% EPROM Interface Min 120 210 0 70 60 0 10 50 60 100 100 10 7 0.4 0.4 0.7 0 0 100 100 Max ns ns ns ns ns ns ns ns ns ns ns ns s sec sec sec ns ns ns Unit Max tWC tPS tCS tWP tDS tDH tCH Write Cycle Time Power Down High to Write Enable Low Chip Enable Low to Write Enable Low Write Enable Low to Write Enable High Data Valid to Write Enable High Write Enable High to Data Transition Write Enable High to Chip Enable High 100 210 0 60 60 0 10 40 60 100 100 10 7 0.4 0.4 0.7 0 0 tWPH Write Enable High to Write Enable Low tAS tPHS tVPS tAH Address Valid to Write Enable High Power Down VHH (Boot Block Unlock) to Write Enable High VPP High to Write Enable High Write Enable High to Address Transition Write Enable High to Output Valid (Word/Byte Program) Write Enable High to Output Valid (Boot Block Erase) Write Enable High to Output Valid (Parameter Block Erase) Write Enable High to Output Valid (Main Block Erase) tPHH Output Valid to Reset/Power Down High Output Valid to VPP Low Reset/Power Down High to Boot Block Relock (5) tWHAX tWHQV1 (2, 3) tWHQV2 (2, 3) tWHQV3 tWHQV4 (2) (2) tQVPH (5) tQVVPL (5) tPHBR (4, 5) Notes: 1. 2. 3. 4. 5. See Figure 3 and Table 8 for timing measurements. Time is measured to Status Register Read giving bit b7 = '1'. For Program or Erase of the Boot Block RP must be at VHH. Time required for Relocking the Boot Block. Sampled only, not 100% tested. 16/38 M28F410, M28F420 Table 18A. Write AC Characteristics, Write Enable Controlled (1) (TA = -40 to 125C; VPP = 12V 5%) M28F410 / 20 -80 Symbol Alt Parameter VCC = 5V 5% SRAM Interface Min tAVAV tPHWL tELWL tWLWH tDVWH tWHDX tWHEH tWHWL tAVWH tPHHWH tVPHWH (5) -90 VCC = 5V 10% EPROM Interface Min 90 210 0 60 60 0 10 40 60 100 100 10 7 0.4 0.4 0.7 0 0 100 100 Max ns ns ns ns ns ns ns ns ns ns ns ns s sec sec sec ns ns ns Unit Max tWC tPS tCS tWP tDS tDH tCH Write Cycle Time Power Down High to Write Enable Low Chip Enable Low to Write Enable Low Write Enable Low to Write Enable High Data Valid to Write Enable High Write Enable High to Data Transition Write Enable High to Chip Enable High 80 210 0 50 50 0 10 30 50 100 100 10 6 0.3 0.3 0.6 0 0 tWPH Write Enable High to Write Enable Low tAS tPHS tVPS tAH Address Valid to Write Enable High Power Down VHH (Boot Block Unlock) to Write Enable High VPP High to Write Enable High Write Enable High to Address Transition Write Enable High to Output Valid (Word/Byte Program) Write Enable High to Output Valid (Boot Block Erase) Write Enable High to Output Valid (Parameter Block Erase) Write Enable High to Output Valid (Main Block Erase) tPHH Output Valid to Reset/Power Down High Output Valid to VPP Low Reset/Power Down High to Boot Block Relock (5) tWHAX tWHQV1 (2, 3) tWHQV2 (2, 3) tWHQV3 tWHQV4 (2) (2) tQVPH (5) tQVVPL (5) tPHBR (4, 5) Notes: 1. 2. 3. 4. 5. See Figure 3 and Table 8 for timing measurements. Time is measured to Status Register Read giving bit b7 = '1'. For Program or Erase of the Boot Block RP must be at VHH. Time required for Relocking the Boot Block. Sampled only, not 100% tested. 17/38 M28F410, M28F420 Table 18B. Write AC Characteristics, Write Enable Controlled (1) (TA = -40 to 125C; VPP = 12V 5%) M28F410 / 420 -100 Symbol Alt Parameter VCC = 5V 10% EPROM Interface Min tAVAV tPHWL tELWL tWLWH tDVWH tWHDX tWHEH tWHWL tAVWH tPHHWH tVPHWH (5) -120 VCC = 5V 10% EPROM Interface Min 120 210 0 70 60 0 10 50 60 100 100 10 7 0.4 0.4 0.7 0 0 100 100 Max ns ns ns ns ns ns ns ns ns ns ns ns s sec sec sec ns ns ns Unit Max tWC tPS tCS tWP tDS tDH tCH Write Cycle Time Power Down High to Write Enable Low Chip Enable Low to Write Enable Low Write Enable Low to Write Enable High Data Valid to Write Enable High Write Enable High to Data Transition Write Enable High to Chip Enable High 100 210 0 60 60 0 10 40 60 100 100 10 7 0.4 0.4 0.7 0 0 tWPH Write Enable High to Write Enable Low tAS tPHS tVPS tAH Address Valid to Write Enable High Power Down VHH (Boot Block Unlock) to Write Enable High VPP High to Write Enable High Write Enable High to Address Transition Write Enable High to Output Valid (Word/Byte Program) Write Enable High to Output Valid (Boot Block Erase) Write Enable High to Output Valid (Parameter Block Erase) Write Enable High to Output Valid (Main Block Erase) tPHH Output Valid to Reset/Power Down High Output Valid to VPP Low Reset/Power Down High to Boot Block Relock (5) tWHAX tWHQV1 (2, 3) tWHQV2 (2, 3) tWHQV3 tWHQV4 (2) (2) tQVPH (5) tQVVPL (5) tPHBR (4, 5) Notes: 1. 2. 3. 4. 5. See Figure 3 and Table 8 for timing measurements. Time is measured to Status Register Read giving bit b7 = '1'. For Program or Erase of the Boot Block RP must be at VHH. Time required for Relocking the Boot Block. Sampled only, not 100% tested. 18/38 PROGRAM OR ERASE tAVAV VALID tAWVH tWHAX A0-A17 E tWHEH tELWL G tWHWL W tWHQV1,2,3,4 tWHDX CMD or DATA tPHHWH Boot Block Unblock STATUS REGISTER tQVPH tWLWH tDVWH Figure 8. Program & Erase AC Waveforms, W Controlled DQ0-DQ15 COMMAND tPHWL RP tVPHWH tQVVPL VPP POWER-UP AND SET-UP COMMAND CONFIRM COMMAND OR DATA INPUT STATUS REGISTER READ AI01284C M28F410, M28F420 Note: Word-wide Address Data shown, for Byte-wide DQ15 becomes A-1. Command Input and Status Register Read output is on DQ0-DQ7 only. 19/38 M28F410, M28F420 Table 19A. Write AC Characteristics, Chip Enable Controlled (1) (TA = 0 to 70C or -40 to 85C; VPP = 12V 5%) M28F410 / 20 -70 Symbol Alt Parameter VCC = 5V 5% SRAM Interface Min tAVAV tPHEL tWLEL tELEH tDVEH tEHDX tEHWH tEHEL tAVEH tPHHEH (5) tVPHEH (5) tEHAX tEHQV1 tEHQV2 (2, 3) -80 VCC = 5V 10% EPROM Interface Min 80 210 0 50 50 0 10 30 50 100 100 10 6 0.3 0.3 0.6 0 0 100 100 Max ns ns ns ns ns ns ns ns ns ns ns ns s sec sec sec ns ns ns Unit Max tWC tPS tCS tWP tDS tDH tCH tWPH tAS tPHS tVPS tAH Write Cycle Time Power Down High to Chip Enable Low Write Enable Low to Chip Enable Low Chip Enable Low to Chip Enable High Data Valid to Chip Enable High Chip Enable High to Data Transition Chip Enable High to Write Enable High Chip Enable High to Chip Enable Low Address Valid to Chip Enable High Power Down VHH (Boot Block Unlock) to Chip Enable High VPP High to Chip Enable High Chip Enable High to Address Transition Chip Enable High to Output Valid (Word/Byte Program) Chip Enable High to Output Valid (Boot Block Erase) Chip Enable High to Output Valid (Parameter Block Erase) Chip Enable High to Output Valid (Main Block Erase) 70 210 0 50 50 0 10 20 50 100 100 10 6 0.3 0.3 0.6 0 0 (2, 3) tEHQV3 (2) tEHQV4 (2) tQVPH tQVVPL (5) (5) tPHH Output Valid to Reset/Power Down High Output Valid to VPP Low Reset/Power Down High to Boot Block Relock tPHBR (4, 5) Notes: 1. 2. 3. 4. 5. See Figure 3 and Table 8 for timing measurements. Time is measured to Status Register Read giving bit b7 = '1'. For Program or Erase of the Boot Block RP must be at VHH. Time required for Relocking the Boot Block. Sampled only, not 100% tested. 20/38 M28F410, M28F420 Table 19B. Write AC Characteristics, Chip Enable Controlled (1) (TA = 0 to 70C or -40 to 85C; VPP = 12V 5%) M28F410 / 420 -100 Symbol Alt Parameter VCC = 5V 10% EPROM Interface Min tAVAV tPHEL tWLEL tELEH tDVEH tEHDX tEHWH tEHEL tAVEH tPHHEH (5) tVPHEH (5) tEHAX tEHQV1 tEHQV2 (2, 3) -120 VCC = 5V 10% EPROM Interface Min 120 210 0 70 60 0 10 50 60 100 100 10 7 0.4 0.4 0.7 0 0 100 100 Max ns ns ns ns ns ns ns ns ns ns ns ns s sec sec sec ns ns ns Unit Max tWC tPS tCS tWP tDS tDH tCH tWPH tAS tPHS tVPS tAH Write Cycle Time Power Down High to Chip Enable Low Write Enable Low to Chip Enable Low Chip Enable Low to Chip Enable High Data Valid to Chip Enable High Chip Enable High to Data Transition Chip Enable High to Write Enable High Chip Enable High to Chip Enable Low Address Valid to Chip Enable High Power Down VHH (Boot Block Unlock) to Chip Enable High VPP High to Chip Enable High Chip Enable High to Address Transition Chip Enable High to Output Valid (Word/Byte Program) Chip Enable High to Output Valid (Boot Block Erase) Chip Enable High to Output Valid (Parameter Block Erase) Chip Enable High to Output Valid (Main Block Erase) 100 210 0 60 60 0 10 40 60 100 100 10 7 0.4 0.4 0.7 0 0 (2, 3) tEHQV3 (2) tEHQV4 (2) tQVPH tQVVPL (5) (5) tPHH Output Valid to Reset/Power Down High Output Valid to VPP Low Reset/Power Down High to Boot Block Relock tPHBR (4, 5) Notes: 1. 2. 3. 4. 5. See Figure 3 and Table 8 for timing measurements. Time is measured to Status Register Read giving bit b7 = '1'. For Program or Erase of the Boot Block RP must be at VHH. Time required for Relocking the Boot Block. Sampled only, not 100% tested. 21/38 M28F410, M28F420 Table 20A. Write AC Characteristics, Chip Enable Controlled (1) (TA = -40 to 125C; VPP = 12V 5%) M28F410 / 20 -80 Symbol Alt Parameter VCC = 5V 5% SRAM Interface Min tAVAV tPHEL tWLEL tELEH tDVEH tEHDX tEHWH tEHEL tAVEH tPHHEH (5) tVPHEH (5) tEHAX tEHQV1 tEHQV2 (2, 3) -90 VCC = 5V 10% EPROM Interface Min 90 210 0 60 60 0 10 40 60 100 100 10 7 0.4 0.4 0.7 0 0 100 100 Max ns ns ns ns ns ns ns ns ns ns ns ns s sec sec sec ns ns ns Unit Max tWC tPS tCS tWP tDS tDH tCH tWPH tAS tPHS tVPS tAH Write Cycle Time Power Down High to Chip Enable Low Write Enable Low to Chip Enable Low Chip Enable Low to Chip Enable High Data Valid to Chip Enable High Chip Enable High to Data Transition Chip Enable High to Write Enable High Chip Enable High to Chip Enable Low Address Valid to Chip Enable High Power Down VHH (Boot Block Unlock) to Chip Enable High VPP High to Chip Enable High Chip Enable High to Address Transition Chip Enable High to Output Valid (Word/Byte Program) Chip Enable High to Output Valid (Boot Block Erase) Chip Enable High to Output Valid (Parameter Block Erase) Chip Enable High to Output Valid (Main Block Erase) 80 210 0 50 50 0 10 30 50 100 100 10 6 0.3 0.3 0.6 0 0 (2, 3) tEHQV3 (2) tEHQV4 (2) tQVPH tQVVPL (5) (5) tPHH Output Valid to Reset/Power Down High Output Valid to VPP Low Reset/Power Down High to Boot Block Relock tPHBR (4, 5) Notes: 1. 2. 3. 4. 5. See Figure 3 and Table 8 for timing measurements. Time is measured to Status Register Read giving bit b7 = '1'. For Program or Erase of the Boot Block RP must be at VHH. Time required for Relocking the Boot Block. Sampled only, not 100% tested. 22/38 M28F410, M28F420 Table 20B. Write AC Characteristics, Chip Enable Controlled (1) (TA = -40 to 125C; VPP = 12V 5%) M28F410 / 420 -100 Symbol Alt Parameter VCC = 5V 10% EPROM Interface Min tAVAV tPHEL tWLEL tELEH tDVEH tEHDX tEHWH tEHEL tAVEH tPHHEH (5) tVPHEH (5) tEHAX tEHQV1 tEHQV2 (2, 3) -120 VCC = 5V 10% EPROM Interface Min 120 210 0 70 60 0 10 50 60 100 100 10 7 0.4 0.4 0.7 0 0 100 100 Max ns ns ns ns ns ns ns ns ns ns ns ns s sec sec sec ns ns ns Unit Max tWC tPS tCS tWP tDS tDH tCH tWPH tAS tPHS tVPS tAH Write Cycle Time Power Down High to Chip Enable Low Write Enable Low to Chip Enable Low Chip Enable Low to Chip Enable High Data Valid to Chip Enable High Chip Enable High to Data Transition Chip Enable High to Write Enable High Chip Enable High to Chip Enable Low Address Valid to Chip Enable High Power Down VHH (Boot Block Unlock) to Chip Enable High VPP High to Chip Enable High Chip Enable High to Address Transition Chip Enable High to Output Valid (Word/Byte Program) Chip Enable High to Output Valid (Boot Block Erase) Chip Enable High to Output Valid (Parameter Block Erase) Chip Enable High to Output Valid (Main Block Erase) 100 210 0 60 60 0 10 40 60 100 100 10 7 0.4 0.4 0.7 0 0 (2, 3) tEHQV3 (2) tEHQV4 (2) tQVPH tQVVPL (5) (5) tPHH Output Valid to Reset/Power Down High Output Valid to VPP Low Reset/Power Down High to Boot Block Relock tPHBR (4, 5) Notes: 1. 2. 3. 4. 5. See Figure 3 and Table 8 for timing measurements. Time is measured to Status Register Read giving bit b7 = '1'. For Program or Erase of the Boot Block RP must be at VHH. Time required for Relocking the Boot Block. Sampled only, not 100% tested. 23/38 24/38 PROGRAM OR ERASE tAVAV VALID tAVEH tEHAX tEHWH tEHEL tEHQV1,2,3,4 tEHDX CMD or DATA tPHHEH Boot Block Unblock STATUS REGISTER tQVPH tVPHEH tQVVPL CONFIRM COMMAND OR DATA INPUT STATUS REGISTER READ AI01285C M28F410, M28F420 A0-A17 W tWLEL G E tELEH tDVEH Figure 9. Program & Erase AC Waveforms, E Controlled DQ0-DQ15 COMMAND tPHEL RP VPP POWER-UP AND SET-UP COMMAND M28F410, M28F420 Table 21. Word/Byte Program, Erase Times (TA = 0 to 70C; VCC = 5V 10% or 5V 5%) Parameter Main Block Program (Byte) Main Block Program (Word) Boot or Parameter Block Erase Main Block Erase Test Conditions Min VPP = 12V 5% VPP = 12V 5% VPP = 12V 5% VPP = 12V 5% M28F410 / 420 Typ 1.2 0.6 1 2.4 Max 4.2 2.1 7 14 sec sec sec sec Unit Table 22. Word/Byte Program, Erase Times (TA = -40 to 85C or -40 to 125C; VCC = 5V 10% or 5V 5%) Parameter Main Block Program (Byte) Main Block Program (Word) Boot or Parameter Block Erase Main Block Erase Test Conditions Min VPP = 12V 5% VPP = 12V 5% VPP = 12V 5% VPP = 12V 5% M28F410 / 420 Typ 1.4 0.7 1.5 3 Max 5 2.5 10.5 18 sec sec sec sec Unit DEVICE OPERATION (cont'd) E Chip Enable. The Chip Enable activates the memory control logic, input buffers, decoders and sense amplifiers. E High de-selects the memory and reduces the power consumption to the standby level. E can also be used to control writing to the command register and to the memory array, while W remains at a low level. Both addresses and data inputs are then latched on the rising edge of E. RP Reset/Power Down. This is a tri-level input which locks the Boot Block from programming and erasure, and allows the memory to be put in deep power down. When RP is High (up to 6.5V maximum) the Boot Block is locked and cannot be programmed or erased. When RP is above 11.4V the Boot Block is unlockedfor programming or erasure. With RP Low the memory is in deep power down, and if RP is within VSS+0.2V the lowest supply current is absorbed. G Output Enable. The Output Enable gates the outputs through the data buffers during a read operation. W Write Enable. It controls writing to the Command Register and Input Address and Data latches. Both Addresses and Data Inputs are latched on the rising edge of W. BYTE Byte/Word Organization Select. This input selects either byte-wide or word-wide organization of the memory. When BYTE is Low the memory is organized x8 or byte-wide and data input/output uses DQ0-DQ7 while A-1 acts as the additional, LSB, of the memory address that multiplexes the upper or lower byte. In the byte-wide organization DQ8-DQ14 are high impedance. When BYTE is High the memory is organized x16 and data input/output uses DQ0-DQ15 with the memory addressed by A0-A17. VPP Program Supply Voltage. This supply voltage is used for memory Programming and Erase. VPP 10% tolerance option is provided for application requiring maximum 100 write and erase cycles. VCC Supply Voltage. It is the main circuit supply. VSS Ground. It is the reference for all voltage measurements. 25/38 M28F410, M28F420 Figure 10. Memory Map, Word-wide Addresses M28F410 TOP BOOT BLOCK A0-A17 3FFFFh 8K BOOT BLOCK 3E000h 3DFFFh 4K PARAMETER BLOCK 3D000h 3CFFFh 4K PARAMETER BLOCK 3C000h 3BFFFh 48K MAIN BLOCK 30000h 2FFFFh 64K MAIN BLOCK 20000h 1FFFFh 64K MAIN BLOCK 10000h 0FFFFh 64K MAIN BLOCK 00000h Word Wide M28F420 BOTTOM BOOT BLOCK A0-A17 3FFFFh 64K MAIN BLOCK 30000h 2FFFFh 64K MAIN BLOCK 20000h 1FFFFh 64K MAIN BLOCK 10000h 0FFFFh 48K MAIN BLOCK 04000h 03FFFh 4K PARAMETER BLOCK 03000h 02FFFh 4K PARAMETER BLOCK 02000h 01FFFh 8K BOOT BLOCK 00000h AI01277 Word Wide Memory Blocks The memory blocks of the M28F410 and M28F420 are shown in Figure 10. The differencebetween the two productsis simply an inversion of the block map to position the Boot Block at the top or bottom of the memory. The selection of the Boot Block at the top or bottom of the memory depends on the microprocessor needs. Each block of the memory can be erased separately, but only by one block at a time. The erase operation is managed by the P/E.C. but can be suspended in order to read from another block and then resumed. Programming and erasure of the memory is disabled when the program supply is at VPPL. For successful programming and erasure the program supply must be at VPPH. The Boot Block provides additional hardware security by use of the RP signal which must be at VHH before any program or erase operation will be executed by the P/E.C. on the Boot Block. Operations Operations are defined as specific bus cycles and signals which allow memory Read, Command Write, Output Disable, Standby, Power Down, and Electronic Signature Read. They are shown in Table 3. Read. Read operations are used to output the contents of the Memory Array, the Status Register or the Electronic Signature. Both Chip Enable E and Output Enable G must be low in order to read the output of the memory. The Chip Enable input also provides power control and should be used for device selection. Output Enable should be used to gate data onto the output independentof the device selection. A read operation will output either a byte or a word depending on the BYTE signal level. WhenBYTE is Low the output byte is on DQ0-DQ7, DQ8-DQ14 are Hi-Z and A-1 is an additional address input. When BYTE is High the output word is on DQ0-DQ15. The data read depends on the previous command written to the memory (see instructions RD, RSR and RSIG). 26/38 M28F410, M28F420 Write. Write operations are used to give Instruction Commands to the memory or to latch input data to be programmed. A write operation is initiated when Chip Enable E is Low and Write Enable W is Low with Output Enable G High. Commands, Input Data and Addresses are latched on the rising edge of W or E. As for the Read operation, when BYTE is Low a byte is input, DQ8-DQ14 are 'don't care' and A-1 is an additional address. When BYTE is High a word is input. Output Disable. The data outputs are high impedance when the Output Enable G is High with Write Enable W High. Standby. The memory is in standby when the Chip Enable E is High. The power consumption is reduced to the standby level and the outputs are high impedance, independent of the Output Enable G or Write Enable W inputs. Power Down. The memory is in Power Down when RP is low. The power consumption is reduced to the Power Down level, and Outputs are in high impedance, independant of the Chip Enable E, Output Enable G or Write Enable W inputs. Electronic Signature. Two codes identifying the manufacturer and the device can be read from the memories, the manufacturer code for SGSTHOMSON is 20h, and the device codes are 0F2h for the M28F410 (Top Boot Block) and 0FAh for the M28F420 (Bottom Boot Block). These codes allow programming equipment or applications to automatically match their interfaceto the characteristics of the particular manufacturer's product. The Electronic Signature is output by a Read Array operation when the voltage applied to A9 is at VID, the manufacturer code is output when the Address input A0 is Low and the device code when this input is High. Other Address inputs are ignored. The codes are output on DQ0-DQ7. When the BYTE signal is High the outputs DQ8-DQ15 output 00h, when Low these outputs are high impedance and Address input A-1 is ignored. The Electronic Signature can also be read, without raising A9 to VID, after giving the memory the instruction RSIG (see below). Instructions and Commands The memories include a Command Interface (C.I.) which latches commands written to the memory. Instructions are made up from one or more commands to perform memory Read, Read Status Register, Read Electronic Signature, Erase, Program, Clear Status Register, Erase Suspend and Erase Resume. These instructions require from 1 to 3 operations, the first of which is always a write operation and is followed by either a further write operation to confirm the first command or a read operation(s) to output data. A Status Register indicates the P/E.C. status Ready or Busy, the suspend/in-progress status of erase operations, the failure/success of erase and program operations and the low/correct value of the Program Supply voltage VPP. The P/E.C. automatically sets bits b3 to b7 and clears bit b6 & b7. It cannot clear bits b3 to b5. The register can be read by the Read Status Register (RSR) instruction and cleared by the Clear Status Register (CLRS) instruction. The meaning of the bits b3 to b7 is shown in Table 7. Bits b0 to b2 are reserved for future use (and should be masked out during status checks). Read (RD) instruction. The Read instruction consists of one write operation giving the command 0FFh. Subsequent read operations will read the addressedmemory array content and output a byte or word depending on the level of the BYTE input. Read Status Register (RSR) instruction. The Read Status Register instruction may be given at any time, including while the Program/Erase Controller is active. It consists of one write operation giving the command 70h.SubsequentRead operations output the contents of the Status Register. The contents of the status register are latched on the falling edge of E or G signals, and can be read until E or G returns to its initial high level. Either E or G must be toggled to VIH to update the latch. Additionally, any read attempt during program or erase operation will automatically output the contents of the Status Register. Read Electronic Signature (RSIG) instruction. This instruction uses 3 operations.It consists of one write operation giving the command 90h followed by two read operations to output the manufacturer and device codes. The manufacturer code, 20h, is output when the address line A0 is Low, and the device code, 0F2h for the M28F410 or 0FAh for the M28F420, when A0 is High. 27/38 M28F410, M28F420 Erase (EE) instruction. This instruction uses two write operations. The first command written is the Erase Set-up command 20h. The second command is the Erase Confirm command 0D0h. During the input of the second command an address of the block to be erased is given and this is latched into the memory. If the second command given is not the Erase Confirm command then the status register bits b4 and b5 are set and the instruction aborts. Read operations output the status register after erasure has started. During the execution of the erase by the P/E.C., the memory accepts only the RSR (Read Status Register) and ES (Erase Suspend) instructions. Status Register bit b7 returns '0' while the erasure is in progress and '1' when it has completed. After completion the Status Register bit b5 returns '1' if there has been an Erase Failure because erasure has not been verified even after the maximum number of erase cycles have been executed. Status Register bit b3 returns '1' if VPP does not remain at VPPH level when the erasure is attempted and/or proceding. VPP must be at V PPH when erasing, erase should not be attempted when VPP < VPPH as the results will be uncertain. If VPP falls below VPPH or RP goes Low the erase aborts and must be repeated, after having cleared the Status Register (CLRS). The Boot Block can only be erased when RP is also at VHH. Program (PG) instruction. This instruction uses two write operations. The first command written is the Program Set-up command 40h (or 10h). A second write operation latches the Address and the Data to be written and starts the P/E.C. Read operations output the status register after the programming has started. Memory programming is only made by writing '0' in place of '1' in a byte or word. During the execution of the programming by the P/E.C., the memory accepts only the RSR (Read Status Register) instruction. The Status Register bit b7 returns '0' while the programming is in progress and '1' when it has completed. After completion the Status register bit b4 returns '1' if there has been a Program Failure. Status Register bit b3 returns a '1' if VPP does not remain at VPPH when programming is attempted and/or during programming. VPP must be at VPPH when programming, programming should not be attempted when VPP < VPPH as the results will be uncertain. Programming aborts if VPP drops below VPPH or RP goes Low. If aborted the data may be incorrect. Then after having cleared the Status Register (CLRS), the memory must be erased and re-programmed. The Boot Block can only be programmed when RP is at VHH. Clear Status Register (CLRS) instruction. The Clear Status Register uses a single write operation which clears bits b3, b4 and b5, if latched to '1' by the P/E.C., to '0'. Its use is necessary before any new operation when an error has been detected. Erase Suspend (ES) instruction. The Erase operation may be suspended by this instruction which consists of writing the command 0B0h. The Status Register bit b6 indicates whether the erase has actually been suspended, b6 = '1', or whether the P/E.C. cycle was the last and the erase is completed, b6 = '0'. During the suspension the memory will respond only to Read (RD), Read Status Register (RSR) or Erase Resume (ER) instructions. Read operations initially output the status register while erase is suspended but, following a Read instruction, data from other blocks of the memory can be read. VPP must be maintained at VPPH while erase is suspended. If VPP does not remain at VPPH or the RP signal goes Low while erase is suspended then erase is aborted while bits b5 and b3 of the status register are set. Erase operation must be repeated after having cleared the status register, to be certain to erase the block. Erase Resume (ER) instruction. If an Erase Suspend instruction was previously executed, the erase operation may be resumed by giving the command 0D0h. The status register bit b6 is cleared when erasure resumes. Read operations output the status register after the erase is resumed. The suggested flow charts for programs that use the programming, erasure and erase suspend/resume features of the memories are shown in Figure 11 to Figure 13. Programming. The memory can be programmed byte-by-byte(or word-by-word in x16 organization). The Program Supply voltage VPP must be applied before program instructions are given, and if the programming is in the Boot Block, RP must also be raised to VHH to unlock the Boot Block. The Program Supply voltage may be applied continuously during programming. The program sequence is started by writing a Program Set-up command (40h) to the Command Interface,this is followed by writing the address and data byte or word to the memory. The Program/Erase Controllerautomaticallystarts and performs the programming after the second write operation, providing that the V PP voltage (and RP voltage if programming the Boot Block) are correct. During the programming the memory status is checked by reading the status register bit b7 which 28/38 M28F410, M28F420 shows the status of the P/E.C. Bit b7 = '1' indicates that programming is completed. A full status check can be made after each byte/word or after a sequence of data has been programmed. The status check is made on bit b3 for any possible VPP error and on bit b4 for any possible programming error. Erase. The memory can be erased by blocks. The Program Supply voltage VPP must be applied before the Erase instruction is given, and if the Erase is of the Boot Block RP must also be raised to VHH to unlock the Boot Block. The Erase sequence is started by writing an Erase Set-up command (20h) to the Command Interface, this is followed by an address in the block to be erased and the Erase Confirm command (0D0h). The Program/Erase Controller automatically starts and performs the block erase, providing the VPP voltage (and the RP voltage if the erase is of the Boot Block) is correct. During the erase the memory status is checked by reading the status register bit b7 which shows the status of the P/E.C. Bit b7 = '1' indicates that erase is completed. A full status check can be made after the block erase by checking bit b3 for any possible VPP error, bits b5 and b6 for any command sequence errors (erase suspended) and bit b5 alone for an erase error. Reset. Note that after any program or erase instruction has completed with an error indication or after any VPP transitions down to VPPL the Command Interface must be reset by a Clear Status Register Instruction before data can be accessed. Automatic Power Saving The M28F410 and M28F420 memories place themselves in a lower power state when not being accessed. Following a Read operation, after a delay equal to the memory access time, the Supply Current is reduced from a typical read current of 25mA (CMOS inputs, word-wide organization) to less than 2mA. Power Down The memories provide a power down control input RP. When this signal is taken to below VSS + 0.2V all internal circuits are switched off and the supply current drops to typically 0.2A and the program current to typically 0.1A. If RP is taken low during a memory read operation then the memory is deselected and the outputs become high impedance. If RP is taken low during a program or erase sequence then it is aborted and the memory content is no longer valid. Recovery from deep power down requires 300ns to a memory read operation, or 210ns to a command write. On return from power down the status register is cleared to 00h. Power Up The Supply voltage VCC and the Program Supply voltage VPP can be applied in any order. The memory Command Interface is reset on power up to Read Memory Array, but a negative transition of Chip Enable E or a change of the addresses is required to ensure valid data outputs. Care must be taken to avoid writes to the memory when VCC is above VLKO and VPP powers up first. Writes can be inhibited by driving either E or W to VIH. The memory is disabled until RP is up to VIH. Supply Rails Normal precautions must be taken for supply voltage decoupling, each device in a system should have the VCC and VPP rails decoupled with a 0.1F capacitor close to the VCC and VSS pins. The PCB trace widths should be sufficient to carry the VPP program and erase currents required. 29/38 M28F410, M28F420 Figure 11. Program Flow-chart and Pseudo Code Start Write 40h Command Write Address & Data PG instruction: - write 40h command - write Address & Data (memory enters read status state after the PG instruction) Read Status Register do: - read status register (E or G must be toggled) NO b7 = 1 YES b3 = 0 YES b4 = 0 YES End while b7 = 1 NO VPP Low Error (1, 2) If b3 = 0, VPP low error: - error handler NO Program Error (1, 2) If b4 = 0, Program error: - error handler AI01278 Notes: 1. Status check of b3 (VPP Low) and b4 (Program Error) can be made after each byte/word programming or after a sequence. 2. If a VPP Low or Program Erase is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations. 30/38 M28F410, M28F420 Figure 12. Erase Flow-chart and Pseudo Code Start Write 20h Command Write Block Address & 0D0h Command Suspend Loop EE instruction: - write 20h command - write Block Address (A12-A17) & command 0D0h (memory enters read status state after the EE instruction) Read Status Register NO Suspend NO YES do: - read status register (E or G must be toggled) if EE instruction given execute suspend erase loop while b7 = 1 b7 = 1 YES b3 = 0 YES b4, b5 = 1 YES b5 = 0 YES End NO VPP Low Error (1) If b3 = 0, VPP low error: - error handler NO Command Sequence Error If b4, b5 = 0, Command Sequence error: - error handler NO Erase Error (1) If b5 = 0, Erase error: - error handler AI01279 Note: 1. If VPP Low or Erase Error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations. 31/38 M28F410, M28F420 Figure 13. Erase Suspend & Resume Flow-chart and Pseudo Code Start Write 0B0h Command ES instruction: - write 0B0h command (memory enters read register state after the ES instruction) do: - read status register (E or G must be toggled) Read Status Register b7 = 1 YES b6 = 1 YES Write 0FFh Command NO while b7 = 1 NO Erase Complete If b6 = 0, Erase completed (at this point the memory wich accept only the RD or ER instruction) RD instruction: - write 0FFh command - one o more data reads from another block Read data from another block Write 0D0h Command ER instruction: - write 0D0h command to resume erasure Erase Continues AI01280 32/38 M28F410, M28F420 Figure 14. Command Interface and Program Erase Controller Flow-diagram (a) WAIT FOR COMMAND WRITE (1) 90h YES BYTE IDENTIFIER NO 70h YES READ STATUS NO 50h YES CLEAR STATUS NO READ ARRAY 40h or 10h YES PROGRAM SET-UP NO 20h YES NO READ STATUS PROGRAM ERASE SET-UP 0FFh YES NO YES READY (2) NO READ STATUS OD0h YES A NO B ERASE COMMAND ERROR AI01286C Notes: 1. If no command is written, the Command Interface remains in its previous valid state. Upon power-up, on exit from power-down or if VCC falls below VLKO, the Command Interface defaults to Read Array mode. 2. P/E.C. status (Ready or Busy) is read on Status Register bit 7. 33/38 M28F410, M28F420 Figure 15. Command Interface and Program Erase Controller Flow-diagram (b) B A ERASE (READ STATUS) YES READY (2) NO NO 0B0h YES READ STATUS ERASE SUSPEND YES READY (2) NO NO ERASE SUSPENDED ? YES READ STATUS YES 70h NO READ STATUS NO 0D0h YES READ ARRAY READ STATUS (ERASE RESUME) AI01287B Note: 2. P/E.C. status (Ready or Busy) is read on Status Register bit 7. 34/38 M28F410, M28F420 ORDERING INFORMATION SCHEME Example: M28F410 -80 X N 1 TR VCC Range F 5V 1 2 Array Org. Top Boot Bottom Boot Temp. Range 1 3 6 0 to 70 C -40 to 125 C -40 to 85 C TR Option Tape & Reel Packing Speed -70 -80 -90 70ns 80ns 90ns Power Supplies blank VCC 10%, VPP 5% X VCC 5%, VPP 5% M N Package SO44 TSOP56 14 x 20mm -100 100ns -120 120ns For a list of available options (V CC Range, Array Organisation, Speed, etc...) refer to the current Memory Shortform catalogue. For further information on any aspect of this device, please contact SGS-THOMSON Sales Office nearest to you. 35/38 M28F410, M28F420 TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20mm Symb Typ A A1 A2 B C D D1 E e L N CP TSOP56 mm Min Max 1.20 0.05 0.95 0.17 0.10 19.80 18.30 13.90 0.50 0.50 0 56 0.10 0.15 1.05 0.27 0.21 20.20 18.50 14.10 0.70 5 0.020 Typ inches Min Max 0.047 0.002 0.037 0.007 0.004 0.780 0.720 0.547 0.020 0 56 0.004 0.006 0.041 0.011 0.008 0.795 0.728 0.555 0.028 5 A2 1 N e E B N/2 D1 D A CP DIE C TSOP-a Drawing is not to scale A1 L 36/38 M28F410, M28F420 SO44 - 44 lead Plastic Small Outline, 525 mils body width Symb Typ A A1 A2 B C D E e H L N CP SO44 mm Min 2.42 0.22 2.25 Max 2.62 0.23 2.35 0.50 0.10 28.10 13.20 1.27 15.90 0.80 3 44 0.10 16.10 0.031 3 0.25 28.30 13.40 0.050 Typ inches Min 0.095 0.009 0.089 Max 0.103 0.010 0.093 0.020 0.004 1.106 0.520 0.010 1.114 0.528 0.626 0.634 44 0.004 A2 B e D A C CP N E 1 H A1 L SO-b Drawing is not to scale 37/38 M28F410, M28F420 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1995 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 38/38 |
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